The inventive concept relates to memory devices, and, more particularly, to memory devices configured to perform training for alignment between a main clock signal and a data clock signal, a memory system including the memory device, and a method of operating the memory device.
Semiconductor memory devices may be memory devices implemented by using semiconductors, such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). The semiconductor memory devices may be broadly classified into volatile memory devices and non-volatile memory devices. As a frequency band for transmitting and receiving data between a memory controller and a memory device increases, a data clock signal having a high frequency may be used to rapidly transmit and receive data. In addition, since it is difficult to increase an operation speed of a memory core included in the memory device due to a structure of the memory core to perform a memory operation, there is a technical limit to increasing a frequency of a main clock signal used to perform the memory operation. Thus, a difference in frequency between the main clock signal and the data clock signal is gradually increasing, and a frequency ratio between the main clock signal and the data clock signal that are provided from each memory controller may have various values. Therefore, research has been conducted into a method of operating a memory device capable of supporting training to enable elaborate alignment between the main clock signal and the data clock signal in an environment in which the frequency ratio of the main clock signal to the data clock signal is different according to each memory controller.